What is I2C?
The I2C protocol was engineered to replace the complexities of separate data bus and address bus lines with a straightforward 2-wire bus connection that would handle the communication between integrated circuits or devices inside microcontroller projects.
Info is sent out serially using one line for data (typically referred to as SDA) and one for clock (known as SCL). The two wires are in an open collector/drain configuration and pulled high employing a resistor, which forms a "wired AND" circuit. A 7-bit addressing scheme is utilized, which can provide the capability to address 112 devices (16 addresses are reserved). The rate of the clock line is mostly restrained by the bus capacitance, which is four hundred pf. The transmission rate is usually 400 kHz, though there are some implementations that run faster.
Even though most systems are arranged such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a master and take over the bus lines for data transference. If one device needs information transferred to or from another module it must wait till it sees no activity on the bus (SDA and SDL are high). It'll then issue a start signal, which causes all the other devices to enter a "listen" mode. The new master will then broadcast the 7 bit binary address of the proposed receiver along with a read / write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always transmitted MSB first. The receiver with the correct address will respond with an acknowledgement pulse. The info byte (or bytes) are then broadcast according to the read / write standing. After each data byte is sent, a confirmation pulse is sent from the receiving end to the broadcasting end. When the transfer has been finished, the master issues a stop signal. This pulls the clock line high followed by the data line, which frees the bus for another transfer.
The master always has total control of the clock (SCL line) during a data transfer, whether or not it is receiving or transmitting information. The slave can slow the clock by holding it low briefly if it is a slow IC. The master can end the data transference at any point by issuing a stop signal, even during the middle of a byte transfer.
Info is sent out serially using one line for data (typically referred to as SDA) and one for clock (known as SCL). The two wires are in an open collector/drain configuration and pulled high employing a resistor, which forms a "wired AND" circuit. A 7-bit addressing scheme is utilized, which can provide the capability to address 112 devices (16 addresses are reserved). The rate of the clock line is mostly restrained by the bus capacitance, which is four hundred pf. The transmission rate is usually 400 kHz, though there are some implementations that run faster.
Even though most systems are arranged such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a master and take over the bus lines for data transference. If one device needs information transferred to or from another module it must wait till it sees no activity on the bus (SDA and SDL are high). It'll then issue a start signal, which causes all the other devices to enter a "listen" mode. The new master will then broadcast the 7 bit binary address of the proposed receiver along with a read / write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always transmitted MSB first. The receiver with the correct address will respond with an acknowledgement pulse. The info byte (or bytes) are then broadcast according to the read / write standing. After each data byte is sent, a confirmation pulse is sent from the receiving end to the broadcasting end. When the transfer has been finished, the master issues a stop signal. This pulls the clock line high followed by the data line, which frees the bus for another transfer.
The master always has total control of the clock (SCL line) during a data transfer, whether or not it is receiving or transmitting information. The slave can slow the clock by holding it low briefly if it is a slow IC. The master can end the data transference at any point by issuing a stop signal, even during the middle of a byte transfer.
About the Author:
Embedded Adventures is an internet site that explores embedded electronics, including devices that can communicate using I2C such as a real time clock module or an air pressure sensor.
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